Cirrus Logic EP93xx - Manual (Page 403)

DS785UM1 10-9
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
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10.1.9.2 Data Transfer Initiation and Termination
The DMA Controller initiates data transfer in the receive direction when:
• A packer unit becomes full
• A packer unit, dependent on the next address access, contains enough data for an
unaligned byte/word access.
The DMA Controller stops data transfers in the receive direction and moves onto the next
buffer when:
• RxEnd signal is asserted to indicate end of received data or received error.
No matter what the alignment up to now, this causes the AHB Master interface to write
any valid data in the receive packer to main memory. If RxEnd signals the end of
received data then all data which is present in the receive packer gets flushed to
memory. If RxEnd signals an error in receive data, and if the ICE bit (Ignore Channel
Error) is not set, then the erroneous byte is not written to memory. Only valid bytes are
written. If ICE bit is set then the erroneous byte is written to memory. The DMA will
update the Channel Status Register, generating a system interrupt which informs the
processor that a new buffer needs to be allocated, and DMA will also indicate
(NEXTBUFFER field) which pair of buffer descriptor registers (MAXCNTx, BASEx)
should be used for the next buffer.
• The number of bytes transferred from a receive peripheral reaches MAXCNTx.
Note: This refers to bytes entering the data packer and not just data transmitted over the AHB
bus (that is, has same effect as RxEnd signal generated by the peripheral). The DMA
Controller asserts RxTC to the peripheral to indicate this condition. The DMA will update
the Channel Status Register, generating a system interrupt, which informs the processor
that a new buffer needs to be allocated and DMA will also indicate (NEXTBUFFER field)
which pair of buffer descriptor registers (MAXCNTx, BASEx) should be used for the next
buffer.
The DMA Controller initiates data transfers in the transmit direction when an Un-packer unit
becomes empty.
The DMA Controller stops data transfer in the transmit direction when:
• TxEnd signal is asserted to indicate that the transfer is the last in the transmit data
stream. Any data remaining in the Un-packer unit is considered invalid and flushed. At
this point, the Channel Status Register will be updated and next buffer defined.
• TxTC signal asserted by DMA Controller to indicate to the peripheral that the transfer is
the last as the byte count limit has been reached. At this point, the Channel Status
Register will be updated and next buffer defined.
• Bursting across buffers cannot be carried out in either transmit or receive directions. The
reason is that buffer pairs may not be contiguous, as required by HTRANS SEQ transfer
type (where address = address of previous transfer + size in bytes).