4 i2s master clock generation – Cirrus Logic EP93xx User Manual

Page 663

DS785UM1

21-7

S Controller

EP93xx User’s Guide

Descriptions” on page 448.) Note that both left and right sample registers must be read

for the I

S controller to consider the location to be free and modify the internal counter.

If the programmer attempts to read from the FIFO while it is empty, the contents that

were last read from the FIFO will be put onto the APB bus. The FIFO read pointer is not
updated and stays pointing to the same location. The FIFO underflow flag in the Global
Control Status register is asserted. (See “Register Descriptions” on page 448.) If this
happens to be the first attempted read by the programmer on the FIFO while the FIFO
is still empty, the contents at FIFO location 0 are put onto the APB bus. These contents

are zero if the I

S controller has been reset previously.

If the I

S controller signals to the FIFO that new stereo sample pairs have been

received and the FIFO is full, the new samples are ignored. The existing contents in
FIFO locations 0 to 7 are not touched. An internal Overflow bit is set, marking the FIFO
pointer location at which the last good data was received (that is, at [current FIFO
pointer location - 1]). When the FIFO pointer eventually points at this location again,
after reading all 7 other FIFO locations, the FIFO overflow flag in the Global Control
Status Register is asserted (and an interrupt is asserted, if enabled). The Status
Register bit (and interrupt) is cleared by reading a left / right stereo sample pair from this
FIFO location.

The data in the FIFO’s is always right justified for word lengths of 16 and 24 bits. The

upper bits will be set to zero by the I

S controller in this case.

The I

S transmit and receive channels should be disabled before modifying the control

registers. Once the new configuration has been set, the channels can be re-enabled
following the specified start order.

The status of each FIFO is reflected in the Global Control Status register. This register

has 5 bits per FIFO that reflect the state of the FIFO. They are:

• Rx0_underflow - Gets set when the programmer reads the FIFO when it is empty.

• Rx0_overflow - Gets set when an Rx overflow has occurred, and the FIFO pointer is

pointing at the last FIFO location where data was received before the overflow
occurred

• Rx0_fifo_empty - Gets set when there are no left and right stereo samples in the

FIFO.

• Rx0_fifo_half_full - Gets set when there are 4 left and right stereo samples or less in

the FIFO.

• Rx0_fifo_full - Gets set when there are 8 left and right stereo samples in the FIFO.

21.4 I

S Master Clock Generation

The following information is required to generate a set of clocks for the I

S controller. The I

port i2s_mstr_clk_cfg is used to supply the Syscon block the necessary control information in