Cirrus Logic EP93xx User Manual

Page 345

DS785UM1

9-43

1/10/100 Mbps Ethernet LAN Controller

EP93xx User’s Guide

RxFCE1:

Rx Flow Control Enable, bit 1. Setting the RxFCE1 bit
causes all receive frames that pass the Individual Address
[1] register to be scanned for flow control format and, if
detected, the Transmit Flow Control Timer register is set
appropriately.

RxFCE0:

Rx Flow Control Enable, bit 0. Setting the RxFCE0 bit
causes all receive frames that pass the Individual Address
[0] register to be scanned for flow control format and, if
detected, the Transmit Flow Control Timer register is set
appropriately.

BCRC:

Buffer CRC. When set, the received CRC is included in
the received frame buffer, and the received frame length
includes the four byte CRC. When clear, neither the
receive buffer nor the receive length includes the CRC.

SRxON:

Serial Receive ON. The receiver is enabled when set.
When clear, no incoming signals are passed through the
receiver. When a frame is being received, and SerRxON is
cleared, then that receive frame is completed. No
subsequent receive frames are allowed until SerRxON is
set again.

RCRCA:

Runt CRC Accept. When set, received frames, which pass
the destination address filter, but are smaller than 64
bytes, and have a CRC error are accepted. However, the
MAC discards any frame of length less than 8 bytes. When
clear, frames received less that 64 bytes in length with
CRC errors are discarded.

RA:

Runt Accept. When set, received frames, which pass the
destination address filter, but are smaller than 64 bytes,
with a good CRC, are accepted. However, the MAC
discards any frame of length less than 8 bytes. When
clear, frames received less that 64 bytes in length, with a
good CRC are discarded.

PA:

Promiscuous Accept. All frames are accepted when set.

BA:

Broadcast Accept. When set, received frames are
accepted with all 1s in the DA.

MA:

Multicast Accept. When set, received frames are accepted
if the DA, when hashed, matches one of the hash table
bits, and the frame is a multicast frame (first bit of
destination address = 1). See Descriptor Processor
Transmit Registers.