Cirrus Logic EP93xx - Manual (Page 86)

3-16 DS785UM1
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
3
3
3
co-processor uses this bit to distinguish between single precision floating point/32-bit
integer numbers (N=0) and double precision floating point/64-bit integer numbers (N=1).
• W : Specifies whether or not a calculated address is written back to a base register (W=1)
or not (W=0). This bit is ignored by the MaverickCrunch co-processor.
• offset : An 8-bit word offset used in address calculations. These bits are ignored by the
MaverickCrunch co-processor.
Table 3-6 , Table 3-7 , Table 3-8 , and Table 3-9 , define the bit values for opcode2, opcode1,
and cp_num for all of the MaverickCrunch instructions.
Table 3-6. LDC/STC Opcode Map
cp num [3:0] Opcode Bits 22 and 20
00 01 10 11
0100
0101 cfstrs
cfstr32
cfldrs
cfldr32
cfstrd
cfstr64
cfldrd
cfldr64
Table 3-7. CDP Opcode Map
op
code
1
[1:0]
cp
num
[3:0] opcode2[2:0]
000 001 010 011 100 101 110 111
00
0100 cfcpys cfcpyd cfcvtds cfcvtsd cfcvt32s cfcvt32d cfcvt64s cfcvt64d
0101 cfsh32
0110 cfmadd32
01
0100 cfmuls cfmuld cfmv32al cfmv32am cfmv32ah cfmv32a cfmv64a cfmv32sc
0101 cfmul32 cfmul64 cfmac32 cfmsc32 cfcvts32 cfcvtd32 cftruncs32 cftruncd32
0110 cfmsub32
10
0100 cfmval32 cfmvam32 cfmvah32 cfmva32 cfmva64 cfmvsc32
0101 cfsh64
0110 cfmadda32
11
0100 cfabss cfabsd cfnegs cfnegd cfadds cfaddd cfsubs cfsubd
0101 cfabs32 cfabs64 cfneg32 cfneg64 cfadd32 cfadd64 cfsub32 cfsub64
0110 cfmsuba32