Timer1control, Timer2control, Timer3control – Cirrus Logic EP93xx User Manual
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DS785UM1
Copyright 2007 Cirrus Logic
Timers
EP93xx User’s Guide
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Timer1Control,
Timer2Control,
Timer3Control
Address:
Timer1 - 0x8081_0008 - Read/Write
Timer2 - 0x8081_0028 - Read/Write
Timer3 - 0x8081_0088 - Read/Write
Reset Value:
0x0000_0000
Definition:
The Control register provides enable/disable and mode configurations for the
timer.
Bit Descriptions:
RSVD:
Reserved. Unknown during a Read operation.
ENABLE:
Timer enable bit. This bit must be set to “1” to enable the
timer. When the timer is disabled, its clock sources are
turned off. Before re-enabling the timer, its Load register
must be written to again.
MODE:
This bit sets the mode of operation of the timer. When set
to 1, the timer is in periodic timer mode and when set to
“0”, the timer is in free running mode.
CLKSEL:
When set to “1”, the 508 kHz clock is selected and when
set to “0”, the 2 kHz clock is selected.
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16
RSVD
15
14
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10
9
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7
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5
4
3
2
1
0
RSVD
ENABLE
MODE
RSVD
CLKSEL
RSVD