Cirrus Logic EP93xx - Manual (Page 490)

12-12 DS785UM1
Copyright 2007 Cirrus Logic
Static Memory Controller
EP93xx User’s Guide
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The number of wait cycles for each of the 2nd, 3rd, and
4th accesses is specified by (WST2 + 1) HCLKs. For
example, if WST2 = 0x4, 4 + 1 = 5 cycles of HCLK are
inserted into the timing for each of the 2nd, 3rd, and 4th
accesses.
On reset, this field defaults to 0x1F (slowest access) to
enable booting from ROM or FLASH memory device
types.
WPERR: Write Protect Error status flag - Read/Write
0 - No Error
1 - Write Protect Error
Writing a ‘1’ to this bit will clear the Write Protect status
error.
WP: Write Protect - Read/Write
The value written to this bit specifies that either Writes to
the memory device are allowed to occur, or not occur:
0 - Yes (SRAM, FLASH)
1 - No (ROM, SRAM, FLASH)
PME: Page Mode (Burst-of-4) Enable - Read/Write
0 - Page Mode is disabled, non-burst accesses occur
1 - Page Mode is enabled. Page Mode provides fast burst-
of-four accesses where the A[3] and A[4] address bits are
internally incremented, ‘00’ –> ‘01’ –> ‘10’ –> ‘11’, to
access four sequential words.
This bit is reset to ‘0’
MW: Memory Width - Read/Write
The value written to this field specifies the bus-width of the
memory:
00 - 8-bit
01 - 16-bit
10 - 32-bit
11 - 32-bit
To support various bus-width memory devices for booting,
the MW field of the
"SMCBCR[7:0]" register can be
automatically configured with the input values on the nCS7
and nCS6 pins, respectively. This takes place following a
power-on reset, but only if the input values on these pins
are: ASDO = ‘0’, Boot[1:0] = ‘00’, EEDAT = ‘1’. and EECLK
= ‘0’.