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Cirrus Logic EP93xx User Manual

Page 680

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21-24

DS785UM1

Copyright 2007 Cirrus Logic

I

2

S Controller

EP93xx User’s Guide

2

1

2

1

21

Bit Descriptions:

RSVD:

Reserved. Unknown During Read. Must be written as “0”.

WL:

Receive Word Length.
00 - 16 bit mode
01 - 24 bit mode
10 - 32 bit mode

I2SRX0En

Address:

0x8082_0064 - Read/Write

Default:

0x0000_0000

D

efinition:

RX0 Channel Enable

Bit Descriptions:

RSVD:

Reserved. Unknown During Read. Must be written as “0”.

i2s_rx0_EN:

RX0 Channel Enable

I2SRX1En

Address:

0x8082_0068 - Read/Write

Default:

0x0000_0000

D

efinition:

RX1 Channel Enable

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RSVD

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RSVD

i2s_rx0_EN

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RSVD

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RSVD

i2s_rx1_EN