Cirrus Logic EP93xx User Manual

Page 541

DS785UM1

14-19

UART1 With HDLC and Modem Control Signals

EP93xx User’s Guide

FE:

Framing Error. When this bit is set to 1, it indicates that the
received character did not have a valid stop bit (a valid
stop bit is “1”). This bit is cleared to 0 by a write to
UART1RXSts. In FIFO mode, this error is associated with
the character at the top of the FIFO.

UART1LinCtrlHigh

Address:

0x808C_0008 - Read/Write

Default:

0x0000_0000

Definition:

UART1 Line Control Register High. UART1LinCtrlHigh, UART1LinCtrlMid and
UART1LinCtrlLow form a single 23-bit wide register (UART1LinCtrl) which is updated on a
single write strobe generated by an UART1LinCtrlHigh write. In order to internally update the
contents of UART1LinCtrlMid or UART1LinCtrlLow, a UART1LinCtrlHigh write must always
be performed at the end.

To update the three registers there are two possible sequences:

• UART1LinCtrlLow write, UART1LinCtrlMid write and UART1LinCtrlHigh write

• UART1LinCtrlMid write, UART1LinCtrlLow write and UART1LinCtrlHigh write.

To update UART1LinCtrlLow or UART1LinCtrlMid only:

• UART1LinCtrlLow write (or UART1LinCtrlMid write) and UART1LinCtrlHigh write.

Bit Descriptions:

RSVD:

Reserved. Unknown During Read.

WLEN:

Number of bits per frame:
11 = 8 bits
10 = 7 bits
01 = 6 bits
00 = 5 bits

RSVD

WLEN

FEN

STP2

EPS

PEN

BRK