Hblankstrtstop – Cirrus Logic EP93xx User Manual
Page 226
7-44
DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
7
7
STRT:
Start - Read/Write
The STRT value is the value of the Horizontal down
counter at which the HACTIVE signal becomes active
(starts). This indicates the start of the active video portion
for the Horizontal line. Please refer to video signalling
timing diagrams in
is an internal block signal. The active video interval is
controlled by the logical OR of VACTIVE and HACTIVE.
HBlankStrtStop
Address: 0x8003_022C
Default: 0x0000_0000
Definition: Horizontal Blank signal Start/Stop register
Bit Descriptions:
RSVD:
Reserved - Unknown during read
STOP:
Stop - Read/Write
The STOP value is the value of the Horizontal down
counter at which the HBLANK signal becomes inactive
(stops). This is used to generate the BLANKn signal that is
used by external devices to indicate the end of the active
video portion for the Horizontal line. Please refer to video
signalling timing diagrams in
HBLANK is an internal clock signal. The BLANKn output is
a logical AND of VBLANK and HBLANK.
STRT
:
Start - Read/Write
The STRT value is the value of the Horizontal down
counter at which the HBLANK signal becomes active
(starts). This is used to generate the BLANKn signal that is
used by external devices to indicate the start of the active
video portion for the Horizontal line. Please refer to video
signalling timing diagrams in
HBLANK is an internal clock signal. The BLANK output is
a logical AND of VBLANK and HBLANK
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
STOP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
STRT