Cirrus Logic EP93xx - Manual (Page 181)

DS785UM1 6-19
Copyright 2007 Cirrus Logic
Vectored Interrupt Controller
EP93xx User’s Guide
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Note: Vectored interrupts are only generated if the interrupt is enabled. The specific interrupt is
enabled in the VICxIntEnable register, and the interrupt is set to generate an IRQ interrupt
in the VICxIntSelect register. This prevents multiple interrupts being generated from a
single request if the controller is incorrectly programmed.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
E: Enables vector interrupt. This bit is cleared to ‘0’ on reset.
IntSource: Selects interrupt source by number. You can select any of
the 32 interrupt sources.