Vlinestep, Regi – Cirrus Logic EP93xx User Manual
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DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
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LEN:
Length - Read/Write
The Length value written to this field specifies, in 32-bit
words, the length of video lines that are scanned to the
display. Please see
“Setting up the LineLength Register”
and
“Memory Setup Example” on page 7-31
The remainder of the last word in a video line may not be
used as long as the blanking time is greater than the
remaining number of pixels. The extra pixels will enter the
video chain, but will exit the pipeline during the blanking
interval. When the end of LEN is reached, STEP in the
register is added to the address for video data.
VLineStep
Address: 0x8003_0038
Default: 0x0000_0000
Definition: Video Line Step Size Register
Bit Descriptions:
RSVD:
Reserved - Unknown during read
STEP:
Step - Read/Write
When the end of the video line is reached (see LEN in
register), the Step value written to this field
(specified in 32-bit words) is added to the address for
every video line that is scanned to the display. Please see
“Memory Setup Example” on page 7-31
.
This allows the screen width to be smaller than the video
image width in SDRAM.
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RSVD
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0
RSVD
STEP