Cirrus Logic EP93xx - Manual (Page 366)

9-64 DS785UM1
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
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GlIntROSts
Address:
0x8001_0068 - Read Only
Chip Reset:
0x0000_0000
Soft Reset:
0x0000_0000
Definition:
General Interrupt Read-Only Status register. This is a read-only version of the
Global Interrupt Status Register.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
INT: Global interrupt read-only status bit. This bit is set
whenever the MACint signal to the interrupt controller is
active.
GlIntFrc
Address:
0x8001_006C - Write Only
Chip Reset:
0x0000_0000
Soft Reset:
0x0000_0000
Definition:
Global Interrupt Force Register. This register allows software to generate an
interrupt.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT RSVD