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DS785UM1
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Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
5
5
5
I2SClkDiv
Address:
0x8093_008C - Read/Write, Software locked
Default:
0x0000_0000
Definition:
Configures the I
2
S block audio clocks MCLK, SCLK, and LRCLK.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
SENA:
Enable audio clock generation.
SLAVE:
I
2
S slave. Configures the I
2
S clock system to operate as a
slave. SCLK and LRCLK are chip inputs. The clock
configuration controls in this register are ignored in slave
mode.
ORIDE:
Override I
2
S master configuration.
1 - Override the SAI_MSTR_CLK_CFG from the I
2
S block
and use the I2SClkDiv Register settings.
0 - Use the I2S SAI_MSTR_CLK_CFG signals.
DROP:
Drop SCLK clocks.
1 - When in 64x mode, drop 8 SCLKs.
0 - Do not drop SCLKs.
SPOL:
SCLK polarity. Defines the SCLK edge that aligns to
LRCLK transitions.
1 - LRCLK transitions on the falling SCLK edge.
0 - LRCLK transitions on the rising SCLK edge.
LRDIV:
LRCLK divide select.
00 - LRCK = SCLK / 32
01 - LRCK = SCLK / 64
10 - LRCK = SCLK / 128
11 - Reserved
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SENA
SLAVE
ORIDE
RSVD
DROP
SPOL
LRDIV
SDIV
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MENA
ESEL
PSEL
RSVD
PDIV
RSVD
MDIV