Cirrus Logic EP93xx - Manual (Page 440)

10-46 DS785UM1
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
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Definition:
DMA Channel Arbitration Register. This bit controls the DMA channel
arbitration.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
CHARB: This bit controls DMA channel arbitration. It is reset to “0”,
thus giving a default setting of internal Memory-to-
Peripheral channels having a higher priority than Memory-
to-Memory channels. This bit can be set to “1” to reverse
the default order, that is, giving M2M transfers a higher
priority than internal M2P.