Cirrus Logic EP93xx User Manual

Page 600

17-4

DS785UM1

IrDA
EP93xx User’s Guide

17.3.2.2.2 The Transmit Process

This section describes the transmission process in detail.

1. Is last transmission complete? - Ensure that the Infrared peripheral is not currently

receiving or transmitting data by reading the RSY (for half-duplex communications) and
TBY bits in the IrFlag register. If either is set, postpone the start of transmission.

2. Disable IrDA - If you are changing Ir mode, first disable Ir. To disable IrDA, first clear

IrCtrl.RXE and IrCtrl.TXE. Secondly, clear the IrEnable.EN field to be “00”.

3. Disabling UART2 for MIR and FIR - For MIR and FIR, disable UART2 by writing “0” to

UART2Ctrl and 0 to IrCtrl.

4. Set up the DMA Engine - If DMA is being used, set up the DMA engine by setting up the

registers of the DMA block.

5. Enabling Clocks - For MIR, set up the MIR clock in MIRClkDiv. Select 0.576 or 1.152

Mbps mode by clearing or setting IrCtrl.BRD. For FIR, enable the FIR clock by setting
PwrCnt.FIR_EN.

6. Select Ir Mode - Select SIR, MIR, or FIR mode by writing the IrEnable.EN bit field to be

“01”, “10”, or “11”.

7. Clear Interrupt Sticky Bits - For MIR, write the MISR register, setting the TFC, TAB, RFL,

and RIL bits to clear them. Then read the IrRIB register to clear the RFC bit. For FIR,
write the FISR register, setting the TFC, TAB, RFL, and RIL bits to clear them. Then
read the IrRIB register to clear the RFC bit.

8. Select Transmit Underrun Action - When DMA is used, the TUS bit should be cleared.

9. Enable Transmit - Set the IrCtrl.TXE Transmit Enable bit. Also set IrCtrl.RXE if receive is

to be enabled. If DMA is used, also set IrDMACR.TXDMAE (and IrDMACR.RXDMAE if
receive is to be enabled).

10.Preloading the Transmit FIFO - Copy the first two full words of data into the transmit

FIFO by writing them into the IrData register. The Ir encode block can hold up to 11
bytes of data (two words in the FIFO plus up to three bytes in the IrDataTail register). If
this is sufficient to hold the complete transmission data packet, DMA will not be needed.
The IrCon.TUS bit should be cleared. This will cause the Ir encoder to correctly send the
CRC and end of frame flag. Note: Prefilling the FIFO must happen immediately after
enabling MIR or FIR. Preloading the FIFO is unnecessary for SIR. Also note that
preloading the FIFO is unnecessary for MIR and FIR if DMA is used.

11.Loading the IrDataTail Register - In the PIO and IRQ case, once the FIFO has been

preloaded, the IrDataTail register can be loaded. The IrDataTail register contains the last
bytes in the frame (1, 2 or 3 bytes left over from the last whole word provided by PIO or
IRQ). Note: If DMA is used, loading the IrDataTail register is unnecessary, as the
IrDataTail register is disabled in that case.

12.Send out the data - If DMA is being used, everything is now enabled for the

transmission process to begin. If PIO or IRQ is being used, data should be written to the
IrData register.