Hclkstrtstop – Cirrus Logic EP93xx User Manual
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Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
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HClkStrtStop
Address: 0x8003_001C
Default: 0x0000_0000
Definition: Horizontal Clock Active Start/Stop register
Note: When horizontal clock gating is required, set the STRT and STOP fields in the
HActiveStrtStop register to the STRT and STOP values in HClkStrtStop + 5. This is a
programming requirement that is easily overlooked.
Bit Descriptions:
RSVD:
Reserved - Unknown during read
STOP:
Stop - Read/Write
The STOP value is the value of the Horizontal down
counter at which the HCLKEN signal becomes inactive
(stops). This indicates the end of the video clock for the
Horizontal frame. Please refer to video signalling timing
diagrams in
. HCLKEN is an
internal clock signal. The SPCLK output is enabled by the
logical AND of VCLKEN and HCLKEN.
STRT:
Start - Read/Write
The STRT value is the value of the Horizontal down
counter at which the HCLKEN signal becomes active
(starts). This indicates the start of the video clock for the
Horizontal frame. Please refer to video signalling timing
diagrams in
. HCLKEN is an
internal clock signal. The SPCLK output is enabled by the
logical AND of VCLKEN and HCLKEN.
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30
29
28
27
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25
24
23
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21
20
19
18
17
16
RSVD
STOP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
STRT