Cirrus Logic EP93xx User Manual

Page 435

DS785UM1

10-41

DMA Controller

EP93xx User’s Guide

to indicate that the external device has requested service.
The STATUS register is written by software to clear the
DREQS status bit, thus causing the DMA to ignore the
request.

For level-sensitive DREQ mode, do not attempt to clear
the DREQS status bit, as the request will keep coming
from the external device. The hardware ensures that a
write to the STATUS register has no effect when in level-
sensitive mode.

BCRx

Address:

BCR0: Channel Base Address + 0x0010 - Read/Write
BCR1: Channel Base Address + 0x0014 - Read/Write

Definition:

The Channel Bytes Count Register contains the number of bytes yet to be
transferred for a given block of data in a M2M transfer. Only the lower 16 bits
are valid.

Bit Descriptions:

RSVD:

Reserved. Unknown During Read.

BCRx:

x = “0” or “1” representing the double buffer per channel.
The BCR register must be loaded with the number of byte
transfers to occur. It decrements on the successful
completion of the address transfer during the write-to-
memory state of the M2M transfer. At least 1 of the BCRx
registers must be programmed to a non-zero value before
the ENABLE bit and the START bit (in the case of
software-trigger M2M mode) are set in the Control register.
Writing to a BCRx register causes a next buffer update,
that is, only the BCR of the buffer descriptor has to be
written to in order to use that buffer since the SAR_BASEx
and DAR_BASEx registers do not have to be continuously
updated.

RSVD

BCRx