3 registers, 3 registers -40, Table 9-3. ethernet register list -40 – Cirrus Logic EP93xx User Manual
Page 342
9-40
DS785UM1
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
10.Wait for TxAct in BMSts to be set and then write the appropriate number of descriptors
remaining in the queue to TXDEnq.
9.3 Registers
Table 9-3. Ethernet Register List
Address
Name
Description
0x8001_0000
RXCtl
MAC Receiver Control Register
0x8001_0004
TXCtl
MAC Transmitter Control Register
0x8001_0008
TestCtl
MAC Test Control Register
0x8001_0010
MIICmd
MAC MII Command Register
0x8001_0014
MIIData
MAC MII Data Register
0x8001_0018
MIISts
MAC MII Status Register
0x8001_0020
SelfCtl
MAC Self Control Register
0x8001_0024
IntEn
MAC Interrupt Enable Register
0x8001_0028
IntStsP
MAC Interrupt Status Preserve Register
0x8001_002C
IntStsC
MAC Interrupt Status Clear Register
0x8001_0030 -
0x8001_0034
Reserved
0x8001_0038
DiagAd
MAC Diagnostic Address Register
0x8001_003C
DiagDa
MAC Diagnostic Data Register
0x8001_0040
GT
MAC General Timer Register
0x8001_0044
FCT
MAC Flow Control Timer Register
0x8001_0048
FCF
MAC Flow Control Format Register
0x8001_004C
AFP
MAC Address Filter Pointer Register
0x8001_0050 -
0x8001_0055
IndAd
MAC Individual Address Register, (shares address
space with HashTbl)
0x8001_0050 -
0x8001_0057
HashTbl
MAC Hash Table Register, (shares address space with
IndAd)
0x8001_0060
GlIntSts
MAC Global Interrupt Status Register
0x8001_0064
GlIntMsk
MAC Global Interrupt Mask Register
0x8001_0068
GlIntROSts
MAC Global Interrupt Read Only Status Register
0x8001_006C
GlIntFrc
MAC Global Interrupt Force Register
0x8001_0070
TXCollCnt
MAC Transmit Collision Count Register
0x8001_0074
RXMissCnt
MAC Receive Miss Count Register
0x8001_0078
RXRuntCnt
MAC Receive Runt Count Register
0x8001_0080
BMCtl
MAC Bus Master Control Register
0x8001_0084
BMSts
MAC Bus Master Status Register
0x8001_0088
RXBCA
MAC Receive Buffer Current Address Register
0x8001_0090
RXDQBAdd
MAC Receive Descriptor Queue Base Address Register
0x8001_0094
RXDQBLen
MAC Receive Descriptor Queue Base Length Register
0x8001_0096
RXDQCurLe
n
MAC Receive Descriptor Queue Current Length
Register
0x8001_0098
RXDCurAdd
MAC Receive Descriptor Current Address Register
0x8001_009C
RXDEnq
MAC Receive Descriptor Enqueue Register
0x8001_00A0
RXStsQBAdd
MAC Receive Status Queue Base Address Register
0x8001_00A4
RXStsQBLen
MAC Receive Status Queue Base Length Register
0x8001_00A6
RXStsQCurL
en
MAC Receive Status Queue Current Length Register