Cirrus Logic EP93xx - Manual (Page 668)

21-12 DS785UM1
Copyright 2007 Cirrus Logic
I 2 S Controller
EP93xx User’s Guide
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21
21.7 Registers
21.7.1 I
2
S TX Registers
Table 21-7 summarizes the register set in the Transmitter. Each of the registers listed are
addressable. The left and right data registers for channels 0, 1 and 2 can be accessed by
both APB and DMA accesses. The remaining registers are concerned with control / status
information and can be only accessed through the APB bus.
Table 21-6. FIFO Flags
FIFO Flag Transmitter Receiver
FIFO empty Interrupt and status bit Status bit.
FIFO full Status Interrupt and status bit
FIFO overflow Sticky bit Interrupt and status bit
FIFO underflow Interrupt and status bit Sticky bit
Table 21-7. I
2
S TX Registers
Address Type Width
Reset
Value
Name Description
0x8082_0010 R/W 32 0x0 I2STX0Lft Left Transmit data register for channel 0
0x8082_0014 R/W 32 0x0 I2STX0Rt Right Transmit data register for channel 0
0x8082_0018 R/W 32 0x0 I2STX1Lft Left Transmit data register for channel 1
0x8082_001C R/W 32 0x0 I2STX1Rt Right Transmit data register for channel 1
0x8082_0020 R/W 32 0x0 I2STX2Lft Left Transmit data register for channel 2
0x8082_0024 R/W 32 0x0 I2STX2Rt Right Transmit data register for channel 2
0x8082_0028 R/W 3 0x0 I2STXLinCtrlData Line Control data register
0x8082_002C R/W 2 0x0 I2STXCtrl Control register
0x8082_0030 R/W 2 0x0 I2STXWrdLen Word Length
0x8082_0034 R/W 1 0x0 I2STX0En TX0 Channel Enable
0x8082_0038 R/W 1 0x0 I2STX1En TX1 Channel Enable
0x8082_003C R/W 1 0x0 I2STX2En TX2 Channel Enable