Rasterswlock – Cirrus Logic EP93xx User Manual
Page 237
DS785UM1
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Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
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PCLKEN:
Pixel Clock Enable - Read/Write
The value written to this bit selects whether the pixel clock
or smart panel clock are output to the SPCLK pin, or not:
0 - SPCLK pin at high impedance
1 - PCLK or SCLK active on SPCLK pin
The PIFEN bit above selects PCLK vs. SCLK.
EN:
Enable Video State Machine - Read/Write
The value written to this bit selects whether the video state
machine is enabled, or not:
0 - Video state machine off
1 - Video state machine enabled
RasterSWLock
Address: 0x8003_007C
Default: 0x0000_0000
Definition: Raster Software Lock register
Bit Descriptions:
RSVD:
Reserved - Unknown during read
SWLCK:
Software Lock - Read/Write
WRITE: Writing 0X0000_00AA to this register will unlock
all locked registers until the next block access.
READ: During a read operation, SWLCK[0] has this
meaning:
1 - Unlocked for current bus access
0 - Locked
The Read feature of the RasterSWLock register is used for
testing the locking function.
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RSVD
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0
RSVD
SWLCK