Cirrus Logic EP93xx User Manual
Page 805
DS785UM1
28-15
Copyright 2007 Cirrus Logic
GPIO Interface
EP93xx User’s Guide
2
8
2
8
28
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
PxINTDB:
Interrupt debounce enable.
RawIntStsX
Address:
RawIntStsA: 0x8084_00A4 - Read Only
RawIntStsB: 0x8084_00C0 - Read Only
RawIntStsF: 0x8084_0060 - Read Only
Definition:
Each bit in the register reports whether an interrupt would be signalled if the interrupt were
enabled for the corresponding port; a set bit indicates that an interrupt would be signalled.
The value reported is unaffected by whether interrupts are enabled or disabled. How a bit is
set depends on the interrupt type. If the interrupt is level sensitive active high, it reflects the
pin value. If level sensitive active low, it reflects the inverse of the pin value. If the interrupt is
edge triggered, the bit latches a one whenever the proper level change occurs. How a bit is
cleared also depends on the interrupt type. When an interrupt is level sensitive, it is cleared
when not asserted. When edge triggered, it is cleared by writing the corresponding bit in
GPIOxEOI. Note that the value of a bit is a debounced value if debouncing is enabled.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
PxINTRS:
Raw Interrupt Status.
IntStsX
Address:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
PxINTRS
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
PxINTS