Table 8-23. pixel mode encoding -30, Blockctrl, Regi – Cirrus Logic EP93xx User Manual
Page 294
8-30
DS785UM1
Copyright 2007 Cirrus Logic
Graphics Accelerator
EP93xx User’s Guide
8
8
8
BLOCKCTRL
Address:
0x8004_0024 - Read/Write
Default:
0x0000_0000
Mask:
0x001F_FFFF
Definition:
Block Function Control Register
Bit Descriptions:
RSVD:
Reserved - Unknown during read
PACKD:
Packed Image Bit - Read/Write
This bit is normally ‘0’ to indicate that the source and
destination images during a Block Copy function are the
same size.
When this bit is '1', the a block transfer image source is
stored in packed format. Packed format indicates that the
source image is not the same dimensions as the
destination image, and that source information transfers
are whole words with the possible exceptions of the
beginning and ending words. This allows images to be
packed into any square configuration of whole words,
including a serial stream.
P:
Bits Per Pixel - Read/Write
The value of this field, as shown in
, specifies
the pixel mode (depth) that is used for Graphics
Accelerator functions. The Raster Engine has a similar
pixel depth field, but it’s value is independent from this P
value and may be either different or the same.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
PACKD
P
ERROR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTEOI
BG
REMAP
D1
D0
M1
M0
SYDIR
SXDIR
DYDIR
DXDIR
LINE
FILL
TRANS
INTEN
EN
Table 8-23. Pixel Mode Encoding
P2
P1
P0
Pixel Mode
0
0
0
not defined
0
0
1
4 bit per pixel
0
1
0
8 bits per pixel