Cirrus Logic EP93xx - Manual (Page 564)

15-6 DS785UM1
Copyright 2007 Cirrus Logic
UART2
EP93xx User’s Guide
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Fuartclk <= 4 x Fpclk
If the IrDA SIR functionality is required, UARTCLK must have a frequency between 2.7 MHz
and 542.7 MHz to ensure that the low-power mode transmit pulse duration complies with the
IrDA SIR specification.
15.3.2 Bus Bandwidth Requirements
There are two basic ways of moving data to and from the UART FIFOs:
• Direct DMA interface - this permits byte-wide access to the UART without using the
APB. The DMA block will pack/unpack individual bytes so that it reads or writes full 32-
bit words rather than individual bytes.
• Accessing the UART via the APB - this requires APB/AHB bus bandwidth. Then, both a
read and write are required for each 8-bit data byte.
Bandwidth requirements also depend on the selected baud rate, character size, parity
selection, number of stop bits, and spacing between characters (if receiving).
For example, assume 115,200 baud, 8-bit characters, even parity, one stop bit, no space
between characters. There are 11 bits per character, so 115,200 / 11 = 10473 characters per
second. If both transmitting and receiving, 20,945 characters per second pass through the
UART. Accessing the UART through the DMA interface requires one access per 32 bits,
implying only 20,945 / 4 = 5,236 AHB accesses per second. Accessing the UART through the
APB requires two accesses per byte, implying 20,945 APB bus accesses.
As another example, assume 230,400 baud (the maximum with a UARTCLK equal to
7.3728 Mhz), 5-bit characters, no parity, one stop bit, and no space between characters.
There are 7 bits per character, so 230400 / 7 = 32,914 characters per second. Simultaneous
transmitting and receiving implies 65829 APB characters per second. Using the DMA
interface would result in 16457 AHB accesses per second, while using the APB to access the
UART leads to 65829 bus accesses per second.