Cirrus Logic EP93xx User Manual

Page 555

DS785UM1

14-33

UART1 With HDLC and Modem Control Signals

EP93xx User’s Guide

Address:

0x808C_021C - Read/Write

Default:

0x0000_0000

Definition:

HDLC Status Register. The TFS and RFS bits in this register are replicas of
bits in the UART status register.

Bit Descriptions:

RSVD:

Reserved. Unknown During Read.

PLLE:

Digital PLL Error. (Read Only)
1 - A frame receive was aborted because the DPLL lost
synchronization with the carrier.
0 - DPLL has not lost carrier during frame reception.
This bit is only valid when set up to receive Manchester-
encoded synchronous HDLC.

Note: This bit reflects the status associated with the last character read from the RX FIFO. It

changes with reads from the RX FIFO.

PLLCC:

Digital PLL Carrier Sense. (Read Only)
1 - DPLL tacked onto a carrier.
0 - DPLL does not sense a carrier.

LNKIDL:

Link Idle. (Read Only)
0 - RX data signal has changed within two bit periods
1 - RX data signal has not changed within two bit periods.
This bit is only valid when set up to receive Manchester-
encoded synchronous HDLC.

CRE:

CRC Error. (Read Only)
0 - No CRC check errors encountered in incoming frame.
1 - CRC calculated on the incoming data does not match
CRC value contained within the received frame. This bit is
set with the last data in the incoming frame along with
EOF.

Note: This bit reflects the status associated with the last character read from the RX FIFO. It

changes with reads from the RX FIFO.

ROR:

Receive FIFO Overrun. (Read Only)
0 - RX FIFO has not overrun.
1 - RX logic attempted to place data in the RX FIFO while
it was full. The most recently read data is the last valid
data before the overrun. The rest of the incoming frame is
dropped. EOF is also set.

Note: This bit reflects the status associated with the last character read from the RX FIFO. It

changes with reads from the RX FIFO.