Cirrus Logic EP93xx - Manual (Page 497)

DS785UM1 13-1
Copyright 2007 Cirrus Logic
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Chapter 13
13 SDRAM, SyncROM, and SyncFLASH Controller
13.1 Introduction
Note: In the EP9301 and 9302 processors, the common address/data bus is 16-bits wide
and the SDRAM, SyncROM, and SyncFLASH synchronous memory controller
supports 16-bit and 8-bit devices.
Note: In the EP9307, EP9312, and EP9315 processors, the common address/data bus is
programmable to be either 16-bits or 32-bits wide and the SDRAM, SyncROM, and
SyncFLASH synchronous memory controller supports 32-bit , 16-bit, and 8-bit
devices.
The SDRAM controller provides a high speed memory interface to single-data-rate SDRAMs,
Synchronous FLASH, and Synchronous ROMs.
The key features of the SDRAM controller are:
• Raster DMA input port for high-bandwidth display refreshing.
• Up to four synchronous memory banks that can be independently configured
• Special configuration bits for Synchronous ROM operation
• Ability to program Synchronous FLASH devices using write and erase commands
• Data is transferred between the controller and the synchronous memory device in quad-
word bursts.
• Programmable for 16 or 32-bit data bus: EP9307, EP9312, and EP9315 processors only
• SDRAM contents are preserved when a “soft” reset is asserted
• Power saving synchronous memory clock enable
13.2 Booting from SyncROM or SyncFLASH
During power-on reset, if the values on the processor pins shown in Table CAUTION: select
either a Synchronous ROM device or Synchronous FLASH device to be used for booting up
the processor, a short configuration sequence is activated and completed before the
processor is released from power-on reset. By default, Synchronous Memory Bank 3,
controlled by device configuration register SDRAMDevCfg[3:0], is used for booting.
For a Synchronous ROM device, the configuration sequence writes RAS = 0x2 and CAS =
0x5 to the SDRAMDevCfg[3:0] register and writes RAS = 0x2, CAS = 0x5, and either Burst