Cirrus Logic EP93xx - Manual (Page 194)

7-12 DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
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data into the unused LSBs of the bus to support the full color intensity range. This part of the
multiplexing circuitry actually occurs before the blink logic stage. Once selected and
conditioned, output data is sent to the pixel shift logic and the YCrCb logic. The data is further
conditioned with blanking in another pipeline operation before being sent to a color DAC.
7.4.7 Pixel Shift Logic
The pixel shifting logic on the output of the Video controller circuitry allows for reduced
external data and clock rates by performing multiple pixel transfers in parallel. The output can
be programmed to transfer a single pixel mapped to an 18-bit pixel output per clock (triple 6
RGB on 18 active data lines), 2 pixels per clock up to 9 bits wide each (18 pixel data lines
active), 4 pixels per clock up to 4 bits wide each (16 pixel data lines active), or 8 pixels per
clock up to 2 bits wide each (16 pixel data lines active). The interface can be programmed to
output 2 2/3 - 3-bit pixels on the lower 8 bits of the bus per pixel clock. The interface can be
programmed to operate in dual scan 2 2/3 pixel mode, placing 2 2/3 pixels from the upper
and lower halves of the screen on the lower 8 bits of the bus and the next 8 bits of the bus per
clock respectively. In dual scan mode, selected by writing DSCAN = ‘1’ to the
“PixelMode”
register, every other pixel in the pipeline is from the other half of the display. Therefore, the
dual scan output transfer modes that are supported are 1 upper/1 lower pixel, 2 upper/2 lower
pixels, and 4 upper/4 lower pixels corresponding to the 2 pixels per clock, 4 pixels per clock
and 8 pixels per clock modes.
Table 7-3 shows output pixel transfer modes based on the shift mode “S” value (shift value)
and the color mode “C” value (color value) in the “PixelMode” register: