Sdramdevcfg[3:0, He sdramdevcfg[3:0] r, Sdramdevcfg[3:0] speci – Cirrus Logic EP93xx User Manual
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DS785UM1
Copyright 2007 Cirrus Logic
SDRAM, SyncROM, and SyncFLASH Controller
EP93xx User’s Guide
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3
1
3
13
Latched nCS[7:6] pins values:
Asynchronous (ASDO = ‘0’)
11 - 32-bit
10 - 32-bit
01 - 16-bit
00 - 8-bit
Synchronous (ASDO = ‘1’)
11 - 32-bit SROM (RAS=2, CAS=5, BL=4)
10 - 32-bit SFLASH (WBM=1, CAS=3, BL=4)
01 - 16-bit SROM (RAS=2, CAS=5, BL=8)
00 - 16-bit SFLASH (WBM=1, CAS=3, BL=4)
Note: 8-bit wide bus is not supported for SyncROM or SyncFLASH.
If booting from Asynchronous ROM, asynchronous memory bank zero (nCS0) is mapped to
address 0x0000_0000. If booting from SyncROM or SyncFLASH, Synchronous Memory
Domain 3 (nSDCS3) is re-mapped to address 0x0000_0000. This re-mapping of nSDCS3
does not change until after the boot process is completed and the processor is reset (not
power-on reset). At that time, nSDCS3 is mapped back to address 0xF000_0000, the
beginning address of Synchronous Memory Domain 3.
SDRAMDevCfg[3:0]
Address:
SDRAMDevCfg0: 0x8006_0010 - Read/Write
SDRAMDevCfg1: 0x8006_0014 - Read/Write
SDRAMDevCfg2: 0x8006_0018 - Read/Write
SDRAMDevCfg3: 0x8006_001C - Read/Write
Default:
0x0122_0008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
Auto
Precharge
RSVD
RasToCas
WBM
CasLat
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
SFConfig
Addr
2K
PAGE
SROMLL
SROM512
Bank
Count
External
Bus
Width
RSVD