Cirrus Logic EP93xx - Manual (Page 340)

9-38 DS785UM1
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
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14.Wait for RxAct (BMSts) to be set, and then enqueue the receive descriptors and status.
This will trigger bus master activity for the descriptor reads.
15.Set the required values for Individual Address and Hash Table.
16.Set the required options in RXCtl and TXCtl, enabling SRxON, and STxON.
17.Set any required options in the PHY, and activate.
18.Enqueue transmit descriptors as required.
9.2.5.1 Interrupt Processing
This is the suggested method for processing an interrupt:
1. Interrupt received from the LAN Controller. This may be determined directly by vectoring
to the interrupt service routine, or in a shared environment by polling the interrupt status
register.
2. Read the Interrupt Status Clear register. Based on the result of the low byte, one or more
of three processes need to run - receive queue processing, transmit queue processing,
or other processing.
9.2.5.2 Receive Queue Processing
1. Read the RXStsQCurAdd. This is the point to which the Host needs to process the
status queue.
2. Read status entries up to the value of RXStsQCurAdd.
3. For each status entry, process the receive data. Set the respective status entry to 0 after
the data has been processed
4. Write the number of statuses processed to the RXStsEnq.
5. Write the number of descriptors returned to the RXDEnq. Writing once to each enqueue
register is more economical on bus cycles than writing once for every descriptor or
status entry. Writing once also avoids any possible delays that may otherwise occur
when the controller has to process multiple accesses to the same descriptor.
9.2.5.3 Transmit Queue Processing
1. Read TXStsQCurAdd. This is the point to which the Host needs to process the status
queue.
2. Read status entries up to the value of the TXStsQCurAdd.
3. For each status entry, free the data buffer.
9.2.5.4 Other Processing
The upper three bytes of the Interrupt Status register provide the specific information related
to the “Other” bit in the LSB. There are a number of bits that relate to the descriptor queues.