Cirrus Logic EP93xx - Manual (Page 78)

3-8 DS785UM1
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
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3.2 Programming Examples
The examples below show two algorithms, each implemented using the standard
programming languages and the MaverickCrunch instruction set.
3.2.1 Example 1
Section 3.2.1.2 , Section 3.2.1.3 , and Section 3.2.1.4 show three coding samples performing
the same operation. Section 3.2.1.1 shows common setup code used by all three samples.
Section 3.2.1.2 shows the program implemented in C code. Section 3.2.1.3 uses ARM
assembly language, accessing the MaverickCrunch with ARM co-processor instructions.
Section 3.2.1.4 uses MaverickCrunch assembly language instructions.
3.2.1.1 Setup Code
ldr r0, =80930000 ; Syscon base address
mov r1, #0xaa ; SW lock key
str r1, [r0, #0xc0] ; unlock by writing key to SysSWLock
register
ldr r1, [r0, #0x80] ; Turn on CPENA bit in DEVCFG register
to
orr r1, r1, #0x00800000 ; enable MaverickCrunch co-processor
str r1, [r0, #0x80] ;
3.2.1.2 C Code
int num = 0;
for(num=0; num < 10; num++)
num = num * 5;
3.2.1.3 Accessing MaverickCrunch with ARM Co-Processor Instructions
ldc p5, c0, [r0, #0x0] ; data section preloaded with 0x0 (“num”)
ldc p5, c1, [r0, #0x4] ; data section preloaded with 0xa
ldc p5, c2, [r0, #0x8] ; data section preloaded with 0x1
ldc p5, c3, [r0, #0xc] ; data section preloaded with 0x5
loop
cdp p5, 1, c0, c0, c3, 0 ; c0 <= c0 * 5
cdp p5, 3, c0, c0, c2, 6 ; c0 <= c0 - 1
mrc p5, 0, r15 c0, c1, 4 ; c0 < 10 ?
blt loop ; yes
stc p5, c0, [r0, #0x0] ; no, store result
3.2.1.4 MaverickCrunch Assembly Language Instructions
cfldr32 c0, [r0, #0x0] ; data section preloaded with 0x0 (“num”)
cfldr32 c1, [r0, #0x4] ; data section preloaded with 0xa
cfldr32 c2, [r0, #0x8] ; data section preloaded with 0x1
cfldr32 c3, [r0, #0xc] ; data section preloaded with 0x5