Intstsp/intstsc – Cirrus Logic EP93xx User Manual
Page 362
9-60
DS785UM1
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
IntStsP/IntStsC
Address:
0x8001_0028, for IntStsP - Read/Write
0x8001_002C, for IntStsC - Read Only
Chip Reset:
0x0000_0000
Soft Reset:
0x0000_0000
Definition:
Interrupt Status Preserve and Clear Registers. The interrupt status bits are set
when the corresponding events occur in the MAC. If the corresponding
interrupt enable bit is set in the interrupt enable register, an interrupt signal will
be generated.
Interrupt status is available at two different offsets: Interrupt Status Preserve
and Interrupt Status Clear. Both offsets are a read of the same storage.
Reading the Interrupt Status register Preserve has no effect on the status in
the register, but writing a 1 to a location in this register clears the status bit,
writing a zero has no effect. Reading the Interrupt Status Clear register clears
all the bits in the register that are accessed as defined by the AHB HSIZE
signal. Therefore a routine which will handle all reported status may read via
the Interrupt Status Clear thereby saving a write operation.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
RWI:
Remote Wake-up Interrupt. The remote wake status is set
when a remote wake-up frame is received, and the
RemoteWakeEn (RXCtl) is set. A remote wake-up frame
must pass the receive destination address filter and have
a contiguous sequence of 6 bytes of FFh followed by 8
repetitions of the Individual Address and be a legal frame
(legal length and good CRC).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
RWI
RxMI
RxBI
RxSQI
TxLEI
ECI
TxUHI
RSVD
MOI
TxCOI
RxROI
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
MIII
PHYSI
TI
AHBE
SWI
RSVD
OTHER
TxSQ
RxSQ
RSVD