Cirrus Logic EP93xx - Manual (Page 516)

13-20 DS785UM1
Copyright 2007 Cirrus Logic
SDRAM, SyncROM, and SyncFLASH Controller
EP93xx User’s Guide
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Writing a ‘1’ to this bit, in combination with the values of
the MRS and LCR bits, cause the Synchronous Memory
controller to issue either NOP or PreALL accesses to
SDRAM devices as shown in
Table 13-4 .
0 - See Table 13-14
1 - See Table 13-14
RefrshTimr
Address: 0x8006_0008 - Read/Write
Default: 0x0000_0080
Table 13-14. Synchronous Memory Command Encoding
Initialize MRS LCR Synchronous Memory Command
1 1 0 Issue NOP to Synchronous Memory
1 0 0 Issue PreALL (Pre-charge All) to SDRAM
0 1 0 Enable access to Synchronous Memory device mode register
0 1 1 Issue command to Synchronous FLASH Memory devices
0 0 1 UNDEFINED. Do not use.
1 0 1 UNDEFINED. Do not use.
1 1 1 UNDEFINED. Do not use.
0 0 0 Normal operation
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Refcnt