Cirrus Logic EP93xx - Manual (Page 395)

DS785UM1 10-1
Copyright 2007 Cirrus Logic
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Chapter 10
10 DMA Controller
10.1 Introduction
The DMA Controller can be used to interface streams from 20 internal peripherals to the
system memory using 10 fully-independent programmable channels that consist of 5 Memory
to Internal Peripheral (M2P) transmit channels and 5 Peripheral to Memory (P2M) receive
channels.
The DMA Controller can also be used to interface streams from Memory to Memory (M2M),
from Memory to Internal Peripheral (M2P), or from Memory to External Peripheral (M2P),
using 2 dedicated M2M channels. External handshake signals are optionally available to
support Memory to/from External Peripheral transfers (M2P/P2M). A software trigger is
available for Memory to Memory transfers, and a hardware trigger is available for Memory to
Internal Peripheral.
On the EP93xx chip the following peripherals may be allocated to the 10 channels.
• I
2
S (which contains 3 Tx and 3 Rx DMA Channels)
• AAC (which contains 3 Tx and 3 Rx DMA Channels)
• UART1 (which contains 1 Tx and 1 Rx DMA Channels)
• UART2 (which contains 1 Tx and 1 Rx DMA Channels)
• UART3 (which contains 1 Tx and 1 Rx DMA Channels)
• IrDA (which contains 1 Tx and 1 Rx DMA Channels)
Each peripheral has it’s own bi-directional DMA bus capable of transferring data in both
directions simultaneously. All memory transfers take place via the main system AHB bus.
SSP and IDE can also use the M2M channels to send or receive data using their memory
mapping to perform transfers.
SSPRx, SSPTx, and IDE have access to DMA M2M hardware transfer requests.
10.1.1 DMA Features List
DMA specific features are:
• Ten fully independent, programmable DMA controller internal M2P/P2M channels (5 Tx
and 5 Rx).
• Two dedicated channels for Memory-to-Memory (M2M) and Memory-to-External
Peripheral Transfers (external M2P/P2M).