Cirrus Logic EP93xx - Manual (Page 547)

DS785UM1 14-25
Copyright 2007 Cirrus Logic
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
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UART1DMACtrl
Address:
0x808C_0028 - Read/Write
Default:
0x0000_0000
Definition:
UART DMA Control Register
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
DMAERR: RX DMA error handing enable. If 0, the RX DMA interface
ignores error conditions in the UART receive section. If 1,
the DMA interface stops and notifies the DMA block when
an error occurs. Errors include break errors, parity errors,
and framing errors.
TXDMAE: TX DMA interface enable. Setting to 1 enables the private
DMA interface to the transmit FIFO.
RXDMAE: RX DMA interface enable. Setting to 1 enables the private
DMA interface to the receive FIFO.
Modem Register Descriptions
UART1ModemCtrl
Address:
0x808C_0100 - Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD DMAERR TXDMAE RXDMAE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD 0 0 0 LOOP OUT2 OUT1 RTS DTR