Parllifout – Cirrus Logic EP93xx User Manual
Page 242
7-60
DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
7
7
ParllIfOut
Address: 0x8003_0058
Default: 0x0000_0000
Definition: Parallel Interface Output/Control Register.
This register, if PIFEN = ‘1’ in the
register, is used to access a
Smart Panel. A Smart Panel has an integrated controller and frame buffer.
Bit Descriptions:
RSVD:
Reserved - Unknown during read
RD:
Read control bit - Write Only
Writing a ‘0’ to this bit location will initiate a parallel
interface write cycle; writing a ‘1’ will initiate a parallel
interface read cycle:
1 - Start Smart Panel write cycle
0 - Start Smart Panel read cycle
DAT:
Data - Write Only
The value written to this field is output on the parallel
interface pins during a write cycle. Writing PIFEN = ‘1’ to
the
register redefines the signals on these
pins for Parallel Interface (Smart Panel) operation:
V_CSYNC --> D7 (Smart Panel)
HSYNC --> D6
BLANK --> D5
P17 --> D4
1
0
0
16 bits per pixel
1
0
1
do not use
1
1
0
24 bits per pixel packed
1
1
1
32 bits per pixel (24 bits per pixel unpacked)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
RD
DAT
Table 7-16. Bits per Pixel Scanned Out (Continued)
P2
P1
P0
Pixel Mode