Cirrus Logic EP93xx - Manual (Page 795)

DS785UM1 28-5
Copyright 2007 Cirrus Logic
GPIO Interface
EP93xx User’s Guide
2
8
2
8
28
Figure 28-3. Signal Connections Within the Enhanced GPIO Port Control Logic
(Ports A, B, F)
28.1.3 Reset
All GPIO registers are initialized on system reset. The data and data direction registers for all
ports (except as noted below) are cleared, configuring them as inputs. Port E[1:0] bits are
used for the LED outputs RDLED and GRLED respectively and are set to drive high. Port
G[3:2] bits are used for SLA[1:0] outputs and are set to drive low. Port G[1:0] bits are used
for EEDAT and EECLK respectively and are set up as inputs. All interrupt control and
debounce registers are cleared.
Enhanced GPIO Ports A, B, and F
DDR OE[7:0] OE
DR DATA DATA[7:0]
EP[7:0]
TISR OE
to PRDATA[7:0]
Register
Read
Select
TESTINPSEL
TESTRDSEL
0
1
1
0
INTEN ENA
INTTYPE1 EDGE
INTTYPE2 POL
DB OE
IN
STA
T
U
S
RA
W
INTERRUPT
CONTROL
LOGIC
CLK
ICLK