Cirrus Logic EP93xx - Manual (Page 534)

14-12 DS785UM1
Copyright 2007 Cirrus Logic
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
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When the last byte of data for a packet is read from the receive FIFO, the HDLC logic sets a
number of bits in the UART1HDLCSts depending on the state of the system and the way the
packet was terminated. In all cases, the RFC bit and EOF bit are set. If the receive FIFO
overflowed while the packet was being received, the ROR bit is also set. If CRC is enabled
and the received CRC does not match the calculated one, the CRE bit is set. The RFC bit is
set and, if UART1HDLCCtrl.RFCEN is set, an interrupt is generated. If the packet was
aborted, the RAB bit is set, and an interrupt generated if the UART1HDLCCtrl.RABEN bit is
set. If using Manchester encoding and the packet was aborted due to losing synchronization
with the encoded clock, the UART1HDLCCtrl.PLLE bit is set.
Besides setting bits in the UART1HDLCSts and possibly causing interrupts, reading the last
byte of a packet also loads the UART1HDLCRXInfoBuf register with data describing the
packet. BRAB, BCRE, BROR, and BPLLE are copied from RAB, CRE, ROR, and PLLE in the
UART1HDLCSts. BFRE is copied from the FE bit in the UART1RXSts. BC is set to the
number of bytes in the packet that were read from the FIFO. Whenever this register is written
by the receiver and has not been read since previously it was previously written, the
UART1HDLCSts.RIL bit is set, and, if UART1HDLCSts.RILEN is set, an interrupt is
generated.
If a new packet is received and the first byte of that packet cannot be written into the receive
FIFO because it has overflowed, the UART1HDLCSts.RFL bit is set and the packet is
discarded. An interrupt is generated if the UART1HDLCCtrl.RFLEN bit is also set.
14.4.5 CRCs
Several bits in the UART1HDLCCtrl determine how CRCs are generated by the transmitter
and processed by the receiver. By setting the CRCE bit, the HDLC transmitter will calculate
and append a CRC to each packet. The CRC may be either 16-bit or 32-bit, depending on the
CRCS bit. Furthermore, it will be inverted prior to transmission if the CRCN bit is set. If CRCs
are enabled, the receiver will expect the same type of CRC that the transmitter sends. It will
automatically calculate the CRC for the received packet in the fly, and if the calculated CRC
does not match the received one, the UART1RXSts.CRE bit will be set when the last byte of
the received packet is read from the UART1Data. The receiver does not pass the CRC to the
CPU unless the CRCApd bit is set.
14.4.6 Address Matching
When address matching is enabled, the HDLC receiver will ignore any packet whose address
does not match the programmed configuration. Address matching is enabled and address
size specified by the UART1HDLCCtrl.AME bits. The UART1HDLCAddMtchVal specifies the
addresses that are compared while the UART1HDLCAddMask controls which bits in each
address are compared If one-byte addressing is used, each byte in UART1HDLCAddMtchVal
specifies an address to match, while the corresponding byte in UART1HDLCAddMask
specifies which bits of each address must match. If two-byte addressing is used, each half-
word in UART1HDLCAddMtchVal specifies an address to match and the corresponding half-
word in UART1HDLCAddMask specifies which bits of each address to match. Hence, up to
four different one-byte addresses and two different two-byte addresses may be specified. An