Cirrus Logic EP93xx - Manual (Page 244)

7-62 DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
7
7
Smart Panel R/W and RS signals must be implemented
via GPIOs and controlled via software. The difference
between the CNT[3:0] value and the ESTRT[3:0] value is
what guarantees set up time for these GPIO signals to the
Smart Panel before the rising edge of the E enable signal
on the E pin.
DAT: Data - Read Only
This parallel interface data is input to the EP93xx
processor from the Smart Panel during a read cycle (see
RD bit in the
ParllIfOut register for read cycle). The D[7:0]
bits from the Smart Panel are loaded into this DAT field,
respectively, on the falling edge of the ‘E’ enable control
signal on the E pin.
Writing PIFEN = ‘1’ to the VideoAttribs register redefines
the signals on these pins for Parallel Interface (Smart
Panel) operation:
V_CSYNC --> D7 (Smart Panel)
HSYNC --> D6
BLANK --> D5
P17 --> D4
P3 --> D3
P[2:0] --> D[2:0]
SPCLK --> E
Smart Panel R/W and RS signals must be implemented
via GPIOs and controlled via software.