Cirrus Logic EP93xx - Manual (Page 574)

15-16 DS785UM1
Copyright 2007 Cirrus Logic
UART2
EP93xx User’s Guide
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5
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5
15
ILPDV: IrDA Low Power Divisor bits [7:0]. 8-bit low-power divisor
value. These bits are cleared to 0 at reset. The divisor
must be chosen so that the relationship
1.42 MHz < IrLPBaud16 < 2.12 MHz is maintained, which
results in a low power pulse duration of 1.41–2.11
μ s
(three times the period of IrLPBaud16). The minimum
frequency of IrLPBaud16 ensures that pulses less than
one period of IrLPBaud16 are rejected, but that pulses
greater than 1.4
μ
s are accepted as valid pulses. Zero is
an illegal value. Programming a zero value will result
in no IrLPBaud16 pulses being generated.
UART2DMACtrl
Address:
0x808D_0028 - Read/Write
Default:
0x0000_0000
Definition:
UART DMA Control Register
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
DMAERR: RX DMA error handing enable. If 0, the RX DMA interface
ignores error conditions in the UART receive section. If “1”,
the DMA interface stops and notifies the DMA block when
an error occurs. Errors include break errors, parity errors,
and framing errors.
TXDMAE: TX DMA interface enable. Setting to “1” enables the
private DMA interface to the transmit FIFO.
RXDMAE: RX DMA interface enable. Setting to “1” enables the
private DMA interface to the receive FIFO.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD DMAERR TXDMAE RXDMAE