Rainbow Electronics ATmega128RFA1 - Manual (Page 91)

91
8266A-MCU Wireless-12/09
ATmega128RFA1
Figure 9-34. TX Power Ramping Control for RF Front-Ends
0 6 8 10
TRX_STATE
SLPTR
PLL_O N
2 12 14 16 18 Length [µ s]
PA buffer
4
PA
PA_BUF_LT
PA_LT
DIG 3
DIG 4
M odulation 1 1 1 1 1 1 0 0 0
BU SY_ TX
The start-up sequence of the individual building blocks of the internal transmitter is
shown in the previous figure. The transmission is actually initiated by writing ‘1’ to
SLPTR. The radio transceiver state changes from PLL_ON to BUSY_TX and the PLL
settles to the transmit frequency within 16 µs (parameter tTR23 at page 42). The
modulation starts 16 µs (parameter tTR10 at page 42) after the SLPTR=1. The PA
buffer and the internal PA are enabled during this time.
The control of an external PA is done via the differential pin pair DIG3 and DIG4.
DIG3 = H / DIG4 = L indicates that the transmission starts and can be used to enable
an external PA. The timing of pins DIG3/DIG4 can be adjusted relative to the start of the
frame and the activation of the internal PA buffer. This is controlled using the register
bits PA_BUF_LT and PA_LT. For details refer to
Figure 9-22 on page 77 .
9.8.5 RX Frame Time Stamping
To determine the exact timing of an incoming frame e.g. for beaconing networks, the
Symbol Counter should be used. SFD Time Stamping is enabled by setting bit SCTSE
of the Symbol Counter Control Register SCCR0. The actual 32 Bit Symbol Counter
value is captured in the SFD Time Stamp register SCTSR at the time, the SFD has
been received. For details see section
"SFD and Beacon Timestamp Generation" on
page 135 .
9.8.6 Configurable Start-Of-Frame Delimiter (SFD)
The SFD is a field indicating the end of the SHR and the start of the packet data. The
length of the SFD is 1 octet (2 symbols). This octet is used for byte synchronization only
and is not included in the Frame Buffer.
The value of the SFD could be changed if it is needed to operate non IEEE 802.15.4
compliant networks. An IEEE 802.15.4 compliant network node does not synchronize to
frames with a different SFD value.
The register SFD_VALUE contains the one octet start-of-frame delimiter (SFD) to
synchronize to a received frame. It is not recommended to set the low-order 4 bits to 0
due to the way the SHR is formed.
9.8.7 Dynamic Frame Buffer Protection
The ATmega128RFA1 continues the reception of incoming frames as long as it is in
any receive state. When a frame was successfully received and stored into the Frame
Buffer, the following frame will overwrite the Frame Buffer content again. To relax the
timing requirements for a Frame Buffer read access the Dynamic Frame Buffer