Rainbow Electronics ATmega128RFA1 - Manual (Page 274)

274
8266A-MCU Wireless-12/09
ATmega128RFA1
18.11.13 ICR1L – Timer/Counter1 Input Capture Register Low Byte
Bit 7 6 5 4 3 2 1 0
NA ($86) ICR1L7:0 ICR1L
Read/Write R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
The Input Capture Register is updated with the counter (TCNT1) value each time an
event occurs on the ICP1 pin or on the Analog Comparator output. The Input Capture
Register can be used for defining the counter TOP value. The Input Capture Register is
16-bit in size. To ensure that both the high and low bytes are read simultaneously when
the CPU accesses these registers, the access is performed using an 8-bit temporary
High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See section "Accessing 16-bit Registers" for details.
• Bit 7:0 – ICR1L7:0 - Timer/Counter1 Input Capture Register Low Byte
18.11.14 TIMSK1 – Timer/Counter1 Interrupt Mask Register
Bit 7 6 5 4 3 2 1 0
NA ($6F) Res1 Res0 ICIE1 Res OCIE1C OCIE1B OCIE1A TOIE1 TIMSK1
Read/Write R R RW R R R RW RW
Initial Value 0 0 0 0 0 0 0 0
• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
• Bit 5 – ICIE1 - Timer/Counter1 Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The
corresponding Interrupt Vector is executed when the ICF1 Flag, located in TIFR1, is
set.
• Bit 4 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
• Bit 3 – OCIE1C - Timer/Counter1 Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter1 Output Compare C Match interrupt is enabled.
The corresponding Interrupt Vector is executed when the OCF1C Flag, located in
TIFR1, is set.
• Bit 2 – OCIE1B - Timer/Counter1 Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled.
The corresponding Interrupt Vector is executed when the OCF1B Flag, located in
TIFR1, is set.
• Bit 1 – OCIE1A - Timer/Counter1 Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled.