Rainbow Electronics ATmega128RFA1 - Manual (Page 458)

458
8266A-MCU Wireless-12/09
ATmega128RFA1
30.6.11 Preventing Flash Corruption
During periods of V
DEVDD
<1.8V, the Flash program can be corrupted because the supply
voltage is too low for the CPU and the Flash to operate properly. These issues are the
same as for board level systems using Flash, and the same design solutions should be
applied.
A Flash program corruption can be caused by two situations when the voltage is too
low. First, a regular write sequence to the Flash requires a minimum voltage to operate
correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply
voltage for executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations
(one is sufficient):
1. If there is no need for a Boot Loader update in the system, program the Boot Loader
Lock bits to prevent any Boot Loader software updates.
2. Keep the AVR RESET active (low) during periods of insufficient power supply
voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the
operating voltage matches the detection level. If not, an external low V
DEVDD
reset
protection circuit can be used. If a reset occurs while a write operation is in progress,
the write operation will be completed under the condition that the power supply
voltage is sufficient.
3. Keep the AVR core in Power-down sleep mode during periods of low V
DEVDD
. This
will prevent the CPU from attempting to decode and execute instructions, effectively
protecting the SPMCSR Register and thus the Flash from unintentional writes.
30.6.12 Programming Time for Flash when Using SPM
The calibrated RC Oscillator is used to time Flash accesses. Table 30-4 below shows
the typical programming time for Flash accesses from the CPU.
Table 30-4. SPM Programming Time
Symbol Min Programming Time Max Programming Time
Flash write (Page Write, and write
Lock bits by SPM)
3.7 ms 4.5 ms
Flash write (Page Erase) 7.3 ms 8.9 ms
30.6.13 Simple Assembly Code Example for a Boot Loader
Assembly Code Example
( 1 )
;-the routine writes one page of data from RAM to Flash
; the first data location in RAM is pointed to by the Y pointer
; the first data location in Flash is pointed to by the Z-pointer
;-error handling is not included
;-the routine must be placed inside the Boot space
; (at least the Do_spm sub routine). Only code inside NRWW section
; can be read during Self-Programming (Page Erase and Page Write).
;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),
; loophi (r25), spmcrval (r20)
; storing and restoring of registers is not included in the routine
; register usage can be optimized at the expense of code size
;-It is assumed that either the interrupt table is moved to the
; Boot loader section or that the interrupts are disabled.