Rainbow Electronics ATmega128RFA1 - Manual (Page 337)

337
8266A-MCU Wireless-12/09
ATmega128RFA1
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator
Clock frequency fosc is shown in the following table.
Table 22-5 SPR Register Bits
Register Bits Value Description
0x00 fosc/4
0x01 fosc/16
0x02 fosc/64
0x03 fosc/128
0x04 fosc/2
0x05 fosc/8
0x06 fosc/32
SPR1:0
0x07 fosc/64
22.4.2 SPSR – SPI Status Register
Bit 7 6 5 4 3 2 1 0
$2D ($4D) SPIF WCOL Res4 Res3 Res2 Res1 Res0 SPI2X SPSR
Read/Write R R R R R R R RW
Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – SPIF - SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if
SPIE in SPCR is set and global interrupts are enabled. The SPIF Flag is also set if the
Slave Select pin is an input and is driven low when the SPI is in Master mode. SPIF is
cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF
set and then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL - Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register
with WCOL set and then accessing the SPI Data Register.
• Bit 5:1 – Res4:0 - Reserved
• Bit 0 – SPI2X - Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when
the SPI is in Master mode. This means that the minimum SCK period will be two CPU
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work
at fosc/4 or lower. The SPI interface on the ATmega128RFA1 is also used for program
memory and EEPROM downloading or uploading. See section "Serial Downloading" for
serial programming and verification.