Rainbow Electronics ATmega128RFA1 - Manual (Page 299)

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8266A-MCU Wireless-12/09
ATmega128RFA1
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying the
counter (TCNT5) while the counter is running introduces a risk of missing a compare
match between TCNT5 and one of the OCR5x Registers. Writing to the TCNT5
Register blocks (removes) the compare match on the following timer clock for all
compare units.
• Bit 7:0 – TCNT5L7:0 - Timer/Counter5 Low Byte
18.11.51 OCR5AH – Timer/Counter5 Output Compare Register A High Byte
Bit 7 6 5 4 3 2 1 0
NA ($129) OCR5AH7:0 OCR5AH
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
The Output Compare Registers contain a 16-bit value that is continuously compared
with the counter value (TCNT5). A match can be used to generate an Output Compare
interrupt. The Output Compare Registers are 16-bit in size. To ensure that both the high
and low bytes are written simultaneously when the CPU writes to these registers, the
access is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16-
bit Registers" for details.
• Bit 7:0 – OCR5AH7:0 - Timer/Counter5 Output Compare Register High Byte
18.11.52 OCR5AL – Timer/Counter5 Output Compare Register A Low Byte
Bit 7 6 5 4 3 2 1 0
NA ($128) OCR5AL7:0 OCR5AL
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
The Output Compare Registers contain a 16-bit value that is continuously compared
with the counter value (TCNT5). A match can be used to generate an Output Compare
interrupt. The Output Compare Registers are 16-bit in size. To ensure that both the high
and low bytes are written simultaneously when the CPU writes to these registers, the
access is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16-
bit Registers" for details.
• Bit 7:0 – OCR5AL7:0 - Timer/Counter5 Output Compare Register Low Byte
18.11.53 OCR5BH – Timer/Counter5 Output Compare Register B High Byte
Bit 7 6 5 4 3 2 1 0
NA ($12B) OCR5BH7:0 OCR5BH
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0