Rainbow Electronics ATmega128RFA1 - Manual (Page 302)

302
8266A-MCU Wireless-12/09
ATmega128RFA1
18.11.59 TIMSK5 – Timer/Counter5 Interrupt Mask Register
Bit 7 6 5 4 3 2 1 0
NA ($73) Res1 Res0 ICIE5 Res OCIE5C OCIE5B OCIE5A TOIE5 TIMSK5
Read/Write R R RW R R R RW RW
Initial Value 0 0 0 0 0 0 0 0
• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
• Bit 5 – ICIE5 - Timer/Counter5 Input Capture Interrupt Enable
The Timer/Counter5 has only limited functionality. It does not have an Input Capture
pin. Therefore this bit has no useful meaning.
• Bit 4 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
• Bit 3 – OCIE5C - Timer/Counter5 Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter5 Output Compare C Match interrupt is enabled.
The corresponding Interrupt Vector is executed when the OCF5C Flag, located in
TIFR5, is set.
• Bit 2 – OCIE5B - Timer/Counter5 Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter5 Output Compare B Match interrupt is enabled.
The corresponding Interrupt Vector is executed when the OCF5B Flag, located in
TIFR5, is set.
• Bit 1 – OCIE5A - Timer/Counter5 Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter5 Output Compare A Match interrupt is enabled.
The corresponding Interrupt Vector is executed when the OCF5A Flag, located in
TIFR5, is set.
• Bit 0 – TOIE5 - Timer/Counter5 Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter5 Overflow interrupt is enabled. The corresponding
Interrupt Vector is executed when the TOV5 Flag, located in TIFR5, is set.
18.11.60 TIFR5 – Timer/Counter5 Interrupt Flag Register
Bit 7 6 5 4 3 2 1 0
$1A ($3A) Res1 Res0 ICF5 Res OCF5C OCF5B OCF5A TOV5 TIFR5
Read/Write R R RW R RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.