Rainbow Electronics ATmega128RFA1 - Manual (Page 188)

188
8266A-MCU Wireless-12/09
ATmega128RFA1
14.2.3 Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of
DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.
14.2.4 Switching Between Input and Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,
PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} =
0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up
enabled state is fully acceptable, as a high-impedant environment will not notice the
difference between a strong high driver and a pull-up. If this is not the case, the PUD bit
in the MCUCR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The
user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state
({DDxn, PORTxn} = 0b11) as an intermediate step.
The following table summarizes the control signals for the pin value.
Table 14-1. Port Pin Configurations
D
D
x
n
P
O
R
T
x
n
P
U
D
(i
n
M
C
U
C
R
)
I/O Pull-up Comment
0 0 X Input No Tri-state (Hi-Z)
0 1 0 Input Yes Pxn will source current if ext. pulled low.
0 1 1 Input No Tri-state (Hi-Z)
1 0 X Output No Output Low (Sink)
1 1 X Output No Output High (Source)
14.2.5 Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through
the PINxn Register bit. As shown in
Figure 14-2 on page 187 , the PINxn Register bit
and the preceding latch constitute a synchronizer. This is needed to avoid meta-stability
if the physical pin changes value near the edge of the internal clock, but it also
introduces a delay.
Figure 14-3 on page 189 shows a timing diagram of the
synchronization when reading an externally applied pin value. The maximum and
minimum propagation delays are denoted t
PD,MAX
and t
PD,MIN
respectively.