9 register description, 1 twbr - twi bit rate register, Atmega128rfa1 – Rainbow Electronics ATmega128RFA1 User Manual
Page 401
401
8266A-MCU Wireless-12/09
ATmega128RFA1
will lose the arbitration. Losing masters will switch to not addressed Slave mode or
wait until the bus is free and transmit a new START condition, depending on
application software action.
•
Two or more masters are accessing different slaves. In this case, arbitration will
occur in the SLA bits. Masters trying to output a one on SDA while another Master
outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to
Slave mode to check if they are being addressed by the winning Master. If
addressed, they will switch to SR or ST mode, depending on the value of the
READ/WRITE bit. If they are not being addressed, they will switch to not addressed
Slave mode or wait until the bus is free and transmit a new START condition,
depending on application software action.
This is summarized in
. Possible status values are given in circles.
Figure 25-21. Possible Status Codes Caused by Arbitration
Own
Address / General Call
received
Arbitration lost in SLA
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
No
Arbitration lost in Data
Direction
Yes
Write
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
Read
B0
68/78
38
SLA
START
Data
STOP
25.9 Register Description
25.9.1 TWBR – TWI Bit Rate Register
Bit
7
6
5
4
3
2
1
0
NA ($B8)
TWBR7:0
TWBR
Read/Write
RW
RW
RW
RW
RW
RW
RW
RW
Initial Value
0
0
0
0
0
0
0
0
The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the
Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on
Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at
least 16 times higher than the SCL frequency.
•
Bit 7:0 – TWBR7:0 - TWI Bit Rate Register Value
The TWBR register selects the division factor for the bit rate generator. The bit rate
generator is a frequency divider which generates the SCL clock frequency in the Master
modes. See section "Bit Rate Generator Unit" for calculating bit rates.