Rainbow Electronics ATmega128RFA1 - Manual (Page 329)

329
8266A-MCU Wireless-12/09
ATmega128RFA1
this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to
be updated with a new value.
• Bit 1 – TCR2AUB - Timer/Counter2 Control Register A Update Busy
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit
becomes set. When TCCR2A has been updated from the temporary storage register,
this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready
to be updated with a new value.
• Bit 0 – TCR2BUB - Timer/Counter2 Control Register B Update Busy
When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit
becomes set. When TCCR2B has been updated from the temporary storage register,
this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready
to be updated with a new value.
21.11.9 GTCCR – General Timer Counter Control register
Bit 7 6 5 4 3 2 1 0
$23 ($43) TSM PSRASY GTCCR
Read/Write RW RW
Initial Value 0 0
• Bit 7 – TSM - Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this
mode the value that is written to the PSRASY and PSRSYNC bits is kept, hence
keeping the corresponding prescaler reset signals asserted. This ensures that the
corresponding Timer/Counters are halted and can be configured to the same value
without the risk of one of them advancing during the configuration. When the TSM bit is
written to zero, the PSRASY and PSRSYNC bits are cleared by hardware and the
Timer/Counters simultaneously start counting.
• Bit 1 – PSRASY - Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally
cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating
in asynchronous mode, the bit will remain one until the prescaler has been reset. The
bit will not be cleared by hardware if the TSM bit is set.