Rainbow Electronics ATmega128RFA1 - Manual (Page 297)

297
8266A-MCU Wireless-12/09
ATmega128RFA1
Register Bits Value Description
0x7 Fast PWM, 10-bit
0x8 PWM, Phase and frequency correct, TOP =
ICRn
0x9 PWM, Phase and frequency correct, TOP =
OCRnA
0xA PWM, Phase correct, TOP = ICRn
0xB PWM, Phase correct, TOP = OCRnA
0xC CTC, TOP = OCRnA
0xD Reserved
0xE Fast PWM, TOP = ICRn
0xF Fast PWM, TOP = OCRnA
• Bit 2:0 – CS52:50 - Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter5
according to the following table. External pin modes cannot be used for the
Timer/Counter5.
Table 18-29 CS5 Register Bits
Register Bits Value Description
0x00 No clock source (Timer/Counter stopped)
0x01 clk_IO/1 (no prescaling)
0x02 clk_IO/8 (from prescaler)
0x03 clk_IO/64 (from prescaler)
0x04 clk_IO/256 (from prescaler)
0x05 clk_IO/1024 (from prescaler)
0x06 Reserved
CS52:50
0x07 Reserved
18.11.48 TCCR5C – Timer/Counter5 Control Register C
Bit 7 6 5 4 3 2 1 0
NA ($122) FOC5A FOC5B FOC5C Res4 Res3 Res2 Res1 Res0 TCCR5C
Read/Write RW RW RW R R R R R
Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – FOC5A - Force Output Compare for Channel A
The FOC5A bit is only active when the WGM53:0 bits specify a non-PWM mode. When
writing a logical one to the FOC5A bit, an immediate compare match is forced. Due to
the limited functionality of the Timer/Counter5 the match has no direct impact on any
output pin. Note that the FOC5A bits are implemented as strobes. Therefore it is the
value present in the COM5A1:0 bits that determine the effect of the forced compare. A
FOC5A strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR5A as TOP. The FOC5A bits are always read
as zero.
• Bit 6 – FOC5B - Force Output Compare for Channel B