Rainbow Electronics ATmega128RFA1 - Manual (Page 481)

481
8266A-MCU Wireless-12/09
ATmega128RFA1
31.8.4 Serial Programming Characteristics
For characteristics of the Serial Programming module see "SPI Timing Characteristics"
on page 504 .
Figure 31-15. Serial Programming Waveforms
MSB
MSB
LSB
LSB
SERIAL CLOCK INPUT
(SCK)
SERIAL DATA INPUT
(MOSI)
(MISO)
SAMPLE
SERIAL DATA OUTPUT
31.9 Programming via the JTAG Interface
Programming through the JTAG interface requires control of the four JTAG specific
pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required.
To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The
device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCR
must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low.
Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are available
for programming. This provides a means of using the JTAG pins as normal port pins in
running mode while still allowing In-System Programming via the JTAG interface. Note
that this technique can not be used when using the JTAG pins for Boundary-scan or
On-chip Debug. In these cases the JTAG pins must be dedicated for this purpose.
During programming the clock frequency of the TCK Input must be less than the
maximum frequency of the chip. The System Clock Prescaler can not be used to divide
the TCK Clock Input into a sufficiently low frequency.
As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.
31.9.1 Programming Specific JTAG Instructions
The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG
instructions useful for programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format.
The text describes which Data Register is selected as path between TDI and TDO for
each instruction.
The Run-Test/Idle state of the TAP-controller is used to generate internal clocks. It can
also be used as an idle state between JTAG sequences. The state machine sequence
for changing the instruction word is shown in
Figure 31-16 on page 482.