5 low leakage voltage regulator control – Rainbow Electronics ATmega128RFA1 User Manual
Page 165
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8266A-MCU Wireless-12/09
ATmega128RFA1
Because the calibration setting is fixed, temperature and load current variations during
the following Deep Sleep period are not regulated out. Thus the output voltage may drift
away from the target value. However the design guarantees that for allowed operating
conditions the output voltage will stay within valid limits. After every wake-up a new
calibration cycle is initiated.
The output driving capability of the Low Leakage Voltage Regulator is limited. Its main
purpose is to provide the leakage current of the connected analog and digital blocks.
At least one full calibration cycle of the Low Leakage Voltage Regulator has to be
completed before the power-chain can be disabled. Therefore if the CPU uses one of
the deep sleep modes “power down” or “power save”, the power-chain is not disabled
before the Low Leakage Voltage Regulator completed this first calibration cycle.
By default the LLVREG automatically starts the calibration after finishing the power-on
reset and the wake-up/start-up procedures (see section
for a detailed description of the Low Leakage Voltage
Regulator).
12.5.5 Low Leakage Voltage Regulator Control
The three register LLCR, LLDRL and LLDRH allow the software to monitor the
calibration process and to modify or correct the calibration results. The automatic
calibration is the normal operation mode. It is an internal process that does not require
any software interaction. Nevertheless the calibration is transparent for the user through
LLCR, LLDRL and LLDRH (control and data register respectively).
Before the device can enter the sleep mode “power down” or “power save” the first
calibration cycle of the Low Leakage Voltage Regulator must be completed to get valid
data in LLDRL and LLDRH. The cycle time t
LLVREG CALIB
is not fixed. It depends on the
temperature, manufacturing process and the frequency of the 128 kHz RC oscillator
(independent of the Watchdog setting).
Systems that require very short power-up times may temporarily disable the calibration
process by setting bit LLENCAL to 0.
The output voltage of the Low Leakage Voltage Regulator in sleep mode will be the
most accurate if constantly calibrated to compensate for any environmental changes
(e.g. temperature). However these changes may be slow enough to skip the calibration
during some power-up cycles (e.g. calibrate only every 10
th
power-up time and use the
old calibration results during all other times).
After the completion of the power-up process the calibration will start automatically if bit
LLENCAL in the control register LLCR is 1 (default). The completion of a calibration
cycle is indicated by the bit LLDONE in that same register. After the first cycle the
calibration will continue to run until either the device goes into a sleep mode (“power
down” or “power save”) or by setting the LLENCAL bit to 0. The output voltage of the
Low Leakage Voltage Regulator is then defined by the values in the data register
LLDRL and LLDRH and by the bits LLTCO and LLSHORT of the control register.
Write access to the three register is granted when the bit LLENCAL is set to 0. The
application software can then modify the calibration results. Higher values in the data
register generate lower output voltages in the sleep modes. In general it is not
recommended nor required to alter the automatically generated calibration result.
The write access to the three register must follow a certain scheme to be successful.
The registers are implemented in the I/O clock domain while the logic of the Low
Leakage Voltage Regulator runs with 64 kHz (clock output of the 128 kHz RC oscillator
divided by 2). It takes at least two 64 kHz clock cycles before the data written to the